Network Interface Design with Advance Network Functionalities for NoC

Network-on-chip (NoC) is an evolving design technology used for growing a packet switched communication infrastructure which contain hundreds of intellectual property (IP) cell in single mutli-processor system on chip (MPSoC). Network interface (NI) is one of the building block which make intellectual property macrocell to be associated to on-chip communication backbone. This work propose the design of network interface macrocell which take care of data packetization/ depacketization to and from NoC and promises successful end to end data delivery. It also include the advanced network functionalities like store and forward (S & F) transmission, error management, ordering handling, security with hardware support. The basic characteristics like flit size, IP bus data size, payload & header FIFO size and frequency & size conversion support can be configured. The features can be added on the top of a basic network interface (NI) core. The work is coded by using verilog and is simulated by Xilinx ISE 13.2.